It is common that electrical assemblies comprise at least one substrate that is used as a structural platform as well as to electrically interconnect one electrical component with another. The substrate is commonly a relatively flat panel that comprises a variety of electrical interconnects that run through, within, and/or upon the panel. Examples of substrates include, but are not limited to, printed circuit boards (PCB), motherboards, and carrier substrates within microelectronic packages.
One long-standing method of attachment of an electrical component to the substrate is the well established process of providing the substrate with metalized through holes, referred to as plated through hole vias, through which corresponding pins on the electrical component are inserted, and subsequently soldered from the opposite side of the substrate. With the advent of new manufacturing technologies that do away with the pins on the electrical component, attempts have been made to affect an interconnection between the electrical interconnects of a “pin-less” electrical component and the plated through bore via.
One method of interconnecting electrical components to a substrate, or one substrate to another substrate, incorporates surface mount technology (SMT). The SMT electrical component replaces the pin or wire contacts with simple, flat SMT electrical interconnects known as land pads. Surface mount technology electrical components are widely used because of their compact size. Examples of SMT electrical components include, but are not limited to, integrated circuit microprocessor assembled in flip chip-ball grid array (FC-BGA) packaging.
FIG. 1 is a cross-sectional view of a VIP substrate 10 which comprises a type of electrical interconnect known in the art as a via-in-pad (VIP) 20. The VIP 20 is a modification of the standard through hole via. The VIP 20 comprises a core through hole 16 extending through the thickness of a substrate core 18 with an electrically conductive liner 21 forming a plated though hole 22. In addition, the electrically conductive liner 21 also forms a VIP bond pad 24 surrounding the mouth of the plated through hole 22 on a portion 13 of a core surface 12 of the substrate core 18.
FIG. 2 is a perspective view of the electrically conductive liner 21 and VIP bond pad 24 shown without the substrate core 18 for clarity. The core through hole 16 extending through the thickness of the substrate core 18 with an electrically conductive liner 21 is also referred to as a via, hence the designation “via-in-pad”. The plated though hole 22 is used as an electrical pathway through the substrate core 18.
The SMT electrical interconnect 9 of a SMT electrical components 8 requires that the electrical interconnect on the surface of the VIP substrate 10 has sufficient surface area to provide for a satisfactory electrical interconnection. The VIP bond pad 24 provides an expanded conductive contact surface to permit interconnection with the SMT electrical interconnect 9 using a interconnect material 28.
The SMT electrical component-to-substrate interconnection is made using a known reflow technique, for example, among others, the controlled collapse chip connection (C4) process. The C4 process is extensively used to interconnect the land pads of a microelectronic die to bond pads on the carrier substrate, but is equally applicable to other SMT electrical component-to-substrate interconnection. Attempts have been made to use the C4 process to interconnect SMT electrical interconnects 9 to VIP bond pads 24.
The C4 process involves providing reflowable electrically conductive interconnect material 28 on each SMT electrical interconnect 9. The SMT electrical component 8 is positioned on top of the VIP substrate 10 such that the interconnect material 28 is in contact with the respective upwardly facing VIP bond pads 24. The assembly is processed at elevated temperature wherein the interconnect material 28 softens and/or melts to form an integral bond with the SMT electrical interconnects 9 and the VIP bond pads 24. Upon cooling, the interconnect material 28 solidifies providing an electrical interconnection between the SMT electrical component 8 and the VIP substrate 10.
Electrical interconnection between the SMT electrical interconnects 9 and the VIP bond pads 24 is not without complications. One complication is the migration of molten interconnect material 28 into the plated though hole 22 by capillary action. If a sufficient amount of interconnect material 28 is drawn away from the VIP bond pad 24 and into the plated though hole 22, there will be insufficient interconnect material 28 to make a proper interconnection.
One process that has been tried in the art to limit the amount of interconnect material 28 migrating into the plated though hole 22 involved plugging it with a soldermask plug 29. Soldermask material is deposited into the plated though hole 22 from the opposite side of the VIP substrate 10 intended to be interconnected. The soldermask plug 29 limits the amount of interconnect material 28 that can flow into the plated though hole 22, as well as blocks the flow out of the other side of the plated though hole 22.
The practice of plugging the opposite end of a plated though hole 22 creates additional problems effecting the electrical interconnection. As the interconnect material 28 is heated to the melting point during the reflow process, volatiles in the soldermask material reach the vapor point and are released as gas. The expanding gas can migrate into the molten interconnect material 28 causing a ballooning effect which may produce a weak or failed interconnection. Further, the ballooned interconnect material 28 can make contact with adjacent VIPs 20 causing an electrical short.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a significant need in the art for substrate and methods for interconnecting SMT electrical components to substrate comprising VIP interconnects that offer relatively high density while providing a relatively high quality interconnection.